Any discussion of the related art throughout this specification should in no way be considered as an admission that such art is widely known or forms part of the common general knowledge in the field.
Resistive change devices and arrays, often referred to as resistance RAMs by those skilled in the art, are well known in the semiconductor and electronics industry. Such devices and arrays, for example, include, but are not limited to, phase change memory, solid electrolyte memory, metal oxide resistance memory, and carbon nanotube memory such as NRAM™.
Resistive change devices and arrays store information by adjusting a resistive change element, typically comprising some material that can be adjusted between a number of non-volatile resistive states in response to some applied stimuli, within each individual array cell between two or more resistive states. For example, each resistive state within a resistive change element cell can correspond to a data value which can be programmed and read back by supporting circuitry within the device or array.
For example, a resistive change element might be arranged to switch between two resistive states: a high resistive state (which might correspond to a logic “0”) and a low resistive state (which might correspond to a logic “1”). In this way, a resistive change element can be used to store one binary digit (bit) of data.
Or, as another example, a resistive change element might be arranged to switch between four resistive states, so as to store two bits of data. Or a resistive change element might be arranged to switch between eight resistive states, so as to store three bits of data. Or a resistive change element might be arranged to switch between 2″ resistive states, so as to store n bits of data.
In some cases, a resistive change element may exhibit a higher error rate when attempting to place it into one of its resistive states compared to other resistive states. This error bias can be substantially large. For example, two-state resistive change element with states SET and RESET may show an error distribution of 80% RESET and 20% SET, wherein RESET errors occur four times as often as SET errors. In such circumstances, it is possible to design an error correction method which takes advantage of this error bias to significantly reduce the reliance on traditional error correction methods.
As arrays of resistive change elements are increasingly used to create flash memories, solid state drives (SSDs), and the like in the current state of the art, there is a growing need for improved error detection and correction algorithms specifically designed for resistive change memory arrays to reduce parity overhead and latency. To this end, the present disclosure provides such improved error correction methods.